mitsubishi lsis 262144-bit (32768-word by 8-bit) cmos static ram mitsubishi electric m5m5256dp,kp,fp,vp,rv -45ll-w,-55ll-w,-70ll-w, -45xl-w,-55xl-w,-70xl-w '97.4.7 package m5m256dp : 28 pin 600 mil dip m5m5256dkp : 28 pin 300 mil dip m5m5256dfp : 28 pin 450 mil sop m5m5256dvp,rv : 28pin 8 x 13.4 mm tsop ?ingle +5v power supply ?o clocks, no refresh ?ata-hold on +2.0v power supply ?irectly ttl compatible : all inputs and outputs ?hree-state outputs : or-tie capability ?oe prevents data contention in the i/o bus ?ommon data i/o ?attery backup capability ?ow stand-by current0.05?(typ.) application small capacity memory units description the m5m5256dp,kp,fp,vp,rv is 262,144-bit cmos static rams organized as 32,768-words by 8-bits which is fabricated using high-performance 3 polysilicon cmos technology. the use of resistive load nmos cells and cmos periphery results in a high density and low power static ram. stand-by current is small enough for battery back-up application. it is ideal for the memory systems which require simple interface. especially the m5m5256dvp,rv are packaged in a 28-pin thin small outline package.two types of devices are available, m5m5256dvp(normal lead bend type package), m5m5256drv(reverse lead bend type package). using both types of devices, it becomes very easy to design a printed circuit board. feature pin configuration (top view) 1 20? (vcc=5.5v) (vcc=5.5v) 5? (max) stand-by (max) active (max) power supply current type m5m5256dp, kp, fp,vp,rv-45ll access time 45ns 55ma m5m5256dp, kp, fp,vp,rv-55ll m5m5256dp, kp, fp,vp,rv-70ll 55ns 70ns m5m5256dp, kp, fp,vp,rv-45xl 45ns m5m5256dp, kp, fp,vp,rv-55xl m5m5256dp, kp, fp,vp,rv-70xl 55ns 70ns 2 (vcc=3.0v, typical) 0.05? (vcc=5.5v) m5m5256dp,kp,fp -w 1 a14 2 a12 4 a6 5 a5 6 a4 7 a3 8 a2 9 a1 10 a0 3 a7 11 dq1 12 dq2 13 dq3 14 gnd 28 vcc 26 a13 25 a8 24 a9 23 a11 21 a10 dq8 18 dq7 17 dq6 16 dq5 15 dq4 27 /w 22 /oe 20 /s 19 m5m5256dvp -w 1 a14 2 a12 4 a6 5 a5 6 a4 7 a3 3 a7 8 a2 9 a1 10 a0 11 dq1 12 dq2 13 dq3 14 gnd vcc 28 a13 26 a8 25 a9 24 a11 23 /w 27 /oe 22 a10 21 dq7 18 dq6 17 dq5 16 dq4 15 /s 20 dq8 19 m5m5256drv -w a14 a12 a6 a5 a4 a3 a7 a2 a1 a0 dq1 dq2 dq3 gnd a10 dq7 dq6 dq5 dq4 vcc a13 a8 a9 a11 /w /oe /s dq8 outline 28p2c-a (dvp) outline 28p2c-b (drv) outline 28p4 (dp) 28p4y (dkp) 28p2w-c (dfp) 28 27 25 24 23 22 26 21 20 19 18 17 16 15 1 3 4 5 6 2 7 8 11 12 13 14 9 10 .com .com .com 4 .com u datasheet
mitsubishi lsis 262144-bit (32768-word by 8-bit) cmos static ram mitsubishi electric m5m5256dp,kp,fp,vp,rv -45ll-w,-55ll-w,-70ll-w, -45xl-w,-55xl-w,-70xl-w '97.4.7 function function table the operation mode of the m5m5256dp,kp,fp,vp,rv is determined by a combination of the device control inputs /s, /w and /oe. each mode is summarized in the function table. a write cycle is executed whenever the low level /w overlaps with the low level /s. the address must be set up before the write cycle and must be stable during the entire cycle. the data is latched into a cell on the trailing edge of /w, /s, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. the output enable /oe directly controls the output stage. setting the /oe at a high level,the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated. mode dq icc /s /w /oe non selection write read stand-by active active active high-impedance d in d out x x l l l l x l h h h h high-impedance 2 a read cycle is executed by setting /w at a high level and /oe at a low level while /s are in an active state. when setting /s at a high level, the chip is in a non-selectable mode in which both reading and writing are disabled. in this mode, the output stage is in a high-impedance state, allowing or-tie with other chips and memory expansion by /s. the power supply current is reduced as low as the stand-by current which is specified as icc3 or icc4, and the memory data can be held at +2v power supply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode. vcc (5v) gnd (0v) 27 20 22 2 3 4 6 5 7 25 26 1 8 9 10 21 23 24 2 12 11 13 15 16 17 18 19 address input buffer row decoder (512 rows x 512 columns) 32768 word x 8bit sense anplifier output buffer data input buffer column decoder address input buffer generator clock a 14 a 13 a 8 a 12 a 6 a 7 a 10 a 0 a 1 a 2 a 3 a 4 a 5 a 11 a 9 /w /oe /s 28 14 dq8 dq7 dq6 dq5 dq4 dq3 dq2 dq1 address input data i/o write control input output enable input chip select input block diagram .com .com .com .com 4 .com u datasheet
mitsubishi lsis 262144-bit (32768-word by 8-bit) cmos static ram mitsubishi electric m5m5256dp,kp,fp,vp,rv -45ll-w,-55ll-w,-70ll-w, -45xl-w,-55xl-w,-70xl-w '97.4.7 3 absolute maximum ratings capacitance (ta=-20~70?, vcc=5v?0%, unless otherwise noted) symbol parameter test conditions pf pf unit max 6 8 typ min limits v i =gnd, v i =25mvrms, f=1mhz v o =gnd,v o =25mvrms, f=1mhz input capacitance output capacitance c i c o dc electrical characteristics (ta=-20~70?, vcc=5v?0%, unless otherwise noted) symbol parameter v v v limits test conditions unit v ua * -3.0v in case of ac ( pulse width 30ns ) note 0: direction for current flowing into an ic is positive (no mark). 1: typical value is one at ta = 25?. 2: c i , c o are periodically sampled and are not 100% tested. ma * -3.0v in case of ac ( pulse width 30ns ) ua ua ma v active supply current (ac, mos level ) icc 1 icc 2 stand-by current icc 4 v ih high-level input voltage v il low-level input voltage i o output current in off-state icc 3 stand-by current v oh1 high-level output voltage 1 i oh =-1ma v oh2 high-level output voltage 2 i oh =-0.1ma v ol low-level output voltage i ol =2ma i i input current v i =0 ~ vcc vcc +0.3 0.8 2.2 -0.3 2.4 3 0.4 50 35 20 5 vcc -0.5 ? 40 25 -ll -xl max typ min parameter supply voltage input voltage output voltage power dissipation operating temperature storage temperature unit v v v mw ? conditions with respect to gnd ta=25? 700 -20~70 -65~150 ratings symbol vcc v i v o p d t opr t stg -0.3 * ~7.0 -0.3 * ~vcc+0.3 0~vcc (max 7.0) /s=v ih ,other inputs=0 ~ vcc /s 3 vcc-0.2v, other inputs=0~vcc /s=v ih or or /oe=v ih , v i/o =0 ~ vcc 45ns 70ns 45 30 55ns ma 55 35 45 25 /s=v il , other inputs=v ih or v il output-open min. cycle 45ns 70ns 50 30 55ns active supply current (ac, ttl level ) /s 0.2v, other inputs<0.2v or >vcc-0.2v output-open min. cycle ? ? 0.1 .com .com .com .com 4 .com u datasheet
mitsubishi lsis 262144-bit (32768-word by 8-bit) cmos static ram mitsubishi electric m5m5256dp,kp,fp,vp,rv -45ll-w,-55ll-w,-70ll-w, -45xl-w,-55xl-w,-70xl-w '97.4.7 4 (2) read cycle (3) write cycle symbol parameter t cr read cycle time address access time unit ns ns ns ns ns ns ns ns ns limits t a (s) t a (oe) t dis (s) t dis (oe) t en (s) t en (oe) t v (a) t a (a) -70ll, xl ac electrical characteristics (ta = -20~70?, vcc=5v?0%, unless otherwise noted ) (1) measurement conditions chip select access time output enable access time output disable time after /s high output disable time after /oe high output enable time after /s low output enable time after /oe low data valid time after address max min input pulse level? ih =2.4v,v il =0.6v input rise and fall time5ns reference levelv oh =v ol =1.5v output loads?ig.1,cl=30pf (-45ll,-45xl ) cl=50pf (-55ll,-55xl ) cl=100pf (-70ll,-70xl ) cl=5pf (for ten,tdis) transition is measured ?00mv from steady state voltage. (for ten,tdis) 55 5 5 10 min 55 55 30 20 20 max 45 5 5 10 min 45 45 25 15 15 max -45ll, xl -55ll, xl 70 5 5 10 70 70 35 25 25 symbol parameter unit ns ns ns ns ns ns ns ns ns ns ns ns limits write cycle time write pulse width address setup time address setup time with respect to /w high chip select setup time data setup time data hold time write recovery time output disable time from /w low output disable time from /oe high output enable time from /w high output enable time from /oe low max min -70ll, xl -45ll, xl -55ll, xl 20 20 max 55 40 0 50 50 25 0 0 5 5 min 15 15 max 45 35 0 40 40 20 0 0 5 5 min t cw t w (w) t su (a) t su (a-wh) t su (s) t su (d) t h (d) t rec (w) t dis (w) t dis (oe) t en (w) t en (oe) 25 25 70 50 0 65 65 30 0 0 5 5 vcc dq c l fig.1 output load 1.8k w 990 w (including scope and jig) .com .com .com .com 4 .com u datasheet
mitsubishi lsis 262144-bit (32768-word by 8-bit) cmos static ram mitsubishi electric m5m5256dp,kp,fp,vp,rv -45ll-w,-55ll-w,-70ll-w, -45xl-w,-55xl-w,-70xl-w '97.4.7 t en (w) 5 read cycle write cycle (/w control mode) (4) timing diagrams data valid (note 3) (note 3) t a (a) t a (s) t v (a) t dis (s) t a (oe) t en (oe) t dis (oe) (note 3) (note 3) t cr t h (d) t su (d) dq 1~8 /s t su (s) /oe t su (a-wh) t en (oe) t dis (oe) (note 3) (note 3) /w t w (w) t rec (w) t su (a) t dis (w) t cw t en (s) /w = "h" level a 0~14 dq 1~8 /s /oe a 0~14 data in stable (note 3) (note 3) .com .com .com .com 4 .com u datasheet
mitsubishi lsis 262144-bit (32768-word by 8-bit) cmos static ram mitsubishi electric m5m5256dp,kp,fp,vp,rv -45ll-w,-55ll-w,-70ll-w, -45xl-w,-55xl-w,-70xl-w '97.4.7 6 write cycle ( /s control mode) t su (s) t rec (w) t h (d) t cw (note 5) (note 3) (note 3) t su (a) (note 4) t su (d) data in stable dq 1~8 /s /w a 0~14 note 3 : hatching indicates the state is "don't care". 5 : if /w goes low simultaneously with or prior to /s, the outputs remain in the high impedance state. 6 : don't apply inverted phase signal externally when dq pin is output mode. 4 : writing is executed in overlap of /s and /w low. 7 : ten, tdis are periodically sampled and are not 100% tested. .com .com .com .com 4 .com u datasheet
mitsubishi lsis 262144-bit (32768-word by 8-bit) cmos static ram mitsubishi electric m5m5256dp,kp,fp,vp,rv -45ll-w,-55ll-w,-70ll-w, -45xl-w,-55xl-w,-70xl-w '97.4.7 7 (3) power down characteristics /s control mode power down characteristics (1) electrical characteristics (ta = -20~70?, vcc=5v?0%, unless otherwise noted) power down set up time power down recovery time (2) timing requirements (ta = -20~70?, vcc=5v?0%, unless otherwise noted ) t su (pd) t rec (pd) symbol parameter ns max typ limits min test conditions unit 0 t cr ns 2.2v t su (pd) 4.5v 2.2v t rec (pd) /s 3 vcc - 0.2v vcc /s symbol parameter v v max typ limits min test conditions unit ua v 2 10 -xl (note 8) 0.05 2 vcc (pd) icc (pd) power down supply voltage power down supply current note7: icc (pd) = 1ua in case of ta = 25? note8: icc (pd) = 0.2ua in case of ta = 25? 2.2 v i (/s) chip select input /s vcc = 3v, / s 3 vcc -0.2v, other inputs=0~vcc -ll (note 7) 4.5v 2.2v v cc(pd) 2v v cc(pd) 2.2v v cc(pd) .com .com .com 4 .com u datasheet
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